MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 570

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
26.3
In addition to the BDM commands that provide access to the processor’s registers and the memory
subsystem, the debug module contains a number of registers. Most of these registers (all except the
PST/DDATA trace buffer) are also accessible (write-only) from the processor’s supervisor programming
model by executing the WDEBUG instruction. Thus, the breakpoint hardware in the debug module can be
read (certain registers) or written by the external development system using the serial debug interface or
written by the operating system running on the processor core. Software is responsible for guaranteeing
that accesses to these resources are serialized and logically consistent. The hardware provides a locking
mechanism in the CSR to allow the external development system to disable any attempted writes by the
processor to the breakpoint registers (setting CSR[IPW]). BDM commands must not be issued during the
processor’s execution of the WDEBUG instruction to configure debug module registers or the resulting
behavior is undefined.
These registers, shown in
implemented bits and unimplemented bits are reserved and must be cleared. These registers are also
accessed through the BDM port by the commands, WRITE_DREG and READ_DREG, described in
Section 26.4.1.5, “BDM Command Set
specifies the register, as shown in
26-6
0x0C
0x0D
0x0E
0x00
0x01
0x02
0x03
0x05
0x06
0x07
0x08
0x09
0x0F
DRc
Memory Map/Register Definition
Configuration/status register (CSR)
Extended Configuration/Status Register (XCSR)
Configuration/Status Register 2 (CSR2)
Configuration/Status Register 3 (CSR3)
BDM address attribute register (BAAR)
Address attribute trigger register (AATR)
Trigger definition register (TDR)
PC breakpoint register 0 (PBR0)
PC breakpoint mask register (PBMR)
Address breakpoint high register (ABHR)
Address breakpoint low register (ABLR)
Data breakpoint register (DBR)
Data breakpoint mask register (DBMR)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table
Register Name
26-4, are treated as 32-bit quantities regardless of the number of
Table 26-4. Debug Module Memory Map
Table
Summary.” These commands contain a 5-bit field, DRc, that
26-4.
Width
(bits)
32
32
32
32
32
32
32
32
32
32
32
32
32
2
2
2
R/W
R/W
R/W
R/W (BDM),
W (CPU)
W (CPU)
W (CPU)
W (CPU)
Access
1
1
1
W
W
W
W
W
W
W
W
W
(BDM),
(BDM),
(BDM),
0x0000_0000
0x0000_0000
0x0000_0000
0x0090_0000
0x0000_0000
0x0000_0000
0x0000_0005
0x0000_0005
0x0000_0000
Reset Value
See Section
Undefined,
Unaffected
Undefined,
Unaffected
Undefined,
Unaffected
Freescale Semiconductor
26.3.10/26-25
26.3.10/26-25
26.3.2/26-10
26.3.3/26-13
26.3.4/26-16
26.3.5/26-17
26.3.6/26-18
26.3.7/26-19
26.3.8/26-22
26.3.8/26-22
26.3.9/26-24
26.3.9/26-24
26.3.1/26-7
Section/
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