MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 165

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
1
2
3
4
5
6
Voltage Regulator / PMC
LP mode for the ADC is invoked by setting ADLPC = 1. ADACK is selected via the ADCCFG[ADICLK] field in the ADC. See
Chapter 21, “Analog-to-Digital Converter (ADC16),”
LVD must be enabled to run in stop if converting the bandgap channel.
CCS clock multiplexor path remains active in stop3/4, although IP functions are not available then.
BLPE refers to the ICS bypassed external low-power state. See
The RESET pin also has a direct connection to the on-chip regulator wakeup input. Asserting this pin low while in stop2
triggers the PMC to wakeup. As a result, the device undergoes a power-on-reset sequence.
The LCD can continue to drive a DISPLAY so long as one of the OSCOUT1 or OSCOUT2 signals into the LCD module is
enabled for operation in Stop modes.
Peripheral
VREF
RAM
SCIx
SPIx
TPM
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 6-4. Peripheral Operation as a Function of Power Mode (continued)
1 kHz osc if
Shutdown.
SoftNoClk
enabled
Stop2
Partial
Off
Off
Off
Off
1 kHz osc if
Regulation.
SoftNoClk
SoftNoClk
SoftNoClk
SoftNoClk
enabled
Stop3
Loose
NoClk
for details.
1 kHz osc on
Regulation
FullNoClk
FullNoClk
FullNoClk
FullNoClk
Stop4
NoClk
Chapter 11, “Internal Clock Source
Full
Mode
1 kHz osc on
SoftNoClk
LPwait
SoftOn
SoftOn
SoftOn
SoftOn
On
1 kHz osc on
FullNoClk
FullOn
FullOn
FullOn
FullOn
Wait
On
(ICS),” for more details.
Modes of Operation
1 kHz osc on
SoftOn
SoftOn
SoftOn
SoftOn
SoftOn
LPrun
On
6-13