MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 253

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The reset state of the INTC_PL6P{7,6} registers disables any request remapping.
10.6.3
As previously mentioned, the notion of a software IACK refers to the ability to query the interrupt
controller near the end of an interrupt service routine (after the current interrupt request has been cleared)
to determine if there are any pending (but currently masked) interrupt requests. If the response to the
software IACK’s byte operand read is non-zero, the service routine uses the value as the vector number of
the highest pending interrupt request and passes control to the appropriate new handler. This process
avoids the overhead of a context restore and RTE instruction execution, followed immediately by another
interrupt exception and context save. In system environments with high rates of interrupt activity, this
mechanism can improve overall system performance noticeably.
To illustrate this concept, consider the following ISR code snippet shown in
This snippet includes the prologue and epilogue for an interrupt service routine as well as code needed to
perform software IACK.
At the entry point (
stack to save the four volatile registers (d0, d1, a0, a1) defined in the ColdFire application binary interface.
After saving these registers, the ISR continues at the alternate entry point.
The software IACK is performed near the end of the ISR, after the source of the current interrupt request
is negated. First, the appropriate memory-mapped byte location in the interrupt controller is read
(PC = 0x5C0). The CF1_INTC module returns the vector number of the highest priority pending request.
If no request is pending, zero is returned. The compare instruction is needed to manage a special case
Freescale Semiconductor
00588: 4fef fff0 lea
0058c: 48d7 0303 movem.l #0x0303,(sp)
00590:
005c0: 71b8 ffe0 mvz.b
005c4: 0c00 0041 cmpi.b
005c8: 6f0a
005ca: 91c8
005cc: 2270 0c00 move.l
005d0: 4ee9 0008 jmp
005d4: 4cd7 0303 movem.l (sp),#0x0303
005d8: 4fef 0010 lea
005dc: 4e73
•
•
Setting INTC_PL6P7 to 20 (0x14), remaps sci1_rx as level 6, priority 7.
Setting INTC_PL6P6 to 21 (0x15), remaps sci1_tx as level 6, priority 6.
....
More on Software IACKs
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
irqxx_entry
align
irqxx_entry:
irqxx_alternate_entry:
irqxx_swiack:
ble.b
sub.l
align
irqxx_exit:
rte
-16(sp),sp
INTC_SWIACK.w,d0
#0x41,d0
irqxx_exit
a0,a0
0(a0,d0.l*4),a1
8(a1)
4
16(sp),sp
4
Figure 10-7. ISR Code Snippet with SWIACK
), there is a two-instruction prologue to allocate space on the supervisor
# allocate stack space
# save d0/d1/a0/a1 on stack
# perform software IACK
# pending IRQ or level 7?
# no pending IRQ, then exit
# clear a0
# fetch pointer from xcpt table
# goto alternate isr entry point
# restore d0/d1/a0/a1
# deallocate stack space
# return from handler
Figure
Interrupt Controller (CF1_INTC)
10-7.
10-17