MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 202

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ColdFire Core
implemented in subsequent ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three
areas:
Table 8-5
see the ColdFire Family Programmer’s Reference Manual.
8.3.2
Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors
differ from the M68000 family because they include:
8-10
1. Enhanced support for byte and word-sized operands
2. Enhanced support for position-independent code
3. Miscellaneous instruction additions to address new functionality
•
•
Move from USP
A simplified exception vector table
Reduced relocation capabilities using the vector-base register
Move to USP
CMPI.{B,W}
Instruction
MVS.{B,W}
MVZ.{B,W}
CMP.{B,W}
BYTEREV
MOV3Q.L
CMPA.W
STLDSR
BITREV
summarizes the instructions added to revision ISA_A to form revision ISA_C. For more details
SATS.L
MOVEI
BSR.L
TAS.B
Bcc.L
FF1
Exception Processing Overview
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
The contents of the destination data register are bit-reversed; that is, new Dn[31] equals old
Dn[0], new Dn[30] equals old Dn[1], ..., new Dn[0] equals old Dn[31].
The contents of the destination data register are byte-reversed; that is, new Dn[31:24] equals
old Dn[7:0], ..., new Dn[7:0] equals old Dn[31:24].
The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending
with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then
loaded with the offset count from bit 31 where the first set bit appears.
Moves 3-bit immediate data to the destination location.
User Stack Pointer → Destination register
Source register → User Stack Pointer
Sign-extends source operand and moves it to destination register.
Zero-fills source operand and moves it to destination register.
Performs saturation operation for signed arithmetic and updates destination register,
depending on CCR[V] and bit 31 of the register.
Performs indivisible read-modify-write cycle to test and set addressed memory byte.
Branch conditionally, longword
Branch to sub-routine, longword
Compare, byte and word
Compare address, word
Compare immediate, byte and word
Move immediate, byte and word to memory using Ax with displacement
Pushes the contents of the status register onto the stack and then reloads the status register
with the immediate data value.
Table 8-5. Instruction Enhancements over Revision ISA_A
Description
Freescale Semiconductor