MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 158

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Modes of Operation
Individual power states are discussed in more detail in the following sections.
6.4
Debug mode functions are managed through the background debug controller (BDC) in the Version 1
ColdFire core. The BDC provides the means for analyzing MCU operation during software development.
The debug interface is used to program a bootloader or user application program into the flash program
memory before the MCU is operated in run mode for the first time. When the MCF51EM256 series are
shipped from the Freescale Semiconductor factory, the flash program memory is erased by default unless
specifically noted, so there is no program that could be executed in run mode until the flash memory is
initially programmed. The debug interface can also be used to erase and reprogram the flash memory after
it has been previously programmed.
See
interface.
6.5
While the MCU is in secure mode, there are severe restrictions on which debug commands can be used.
In this mode, only the upper byte of the core’s XCSR, CSR2, and CSR3 registers can be accessed. See
Chapter 26, “Version 1 ColdFire Debug (CF1_DEBUG),”
6-6
1
Chapter 26, “Version 1 ColdFire Debug (CF1_DEBUG),”
An analog connection from this pin to the on-chip regulator wakes up the regulator, which then initiates a
power-on-reset sequence.
Transition #
Debug Mode
Secure Mode
10
11
8
9
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Stop3
Stop4
From
Wait
Run
Halt
Halt
Run
Halt
Table 6-2. Triggers for State Transition (continued)
Stop3
Stop4
Wait
Run
Halt
Run
Halt
Halt
To
for details.
Interrupt when SPMSC2[LPWUI]=1
Pre-configure settings shown in
STOP instruction. The LP bit does not have to be
set prior to entering stop3 in this fashion. But low
voltage interrupts and BDM must be disabled.
When a BACKGROUND command is received
through the BKGD/MS pin (XCSR[ENBDM] must
equal one).
Not supported.
GO instruction issued via BDM
When a BACKGROUND command is received
through the BKGD/MS pin OR
When a HALT instruction is executed OR
When encountering a BDM breakpoint
When a BACKGROUND command is received
through the BKGD/MS pin (XCSR[ENBDM] must
equal one).
Not supported.
for more details regarding the debug
Trigger
Freescale Semiconductor
Table
6-1, execute