MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 193

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 8
ColdFire Core
8.1
This section describes the organization of the Version 1 (V1) ColdFire
of the program-visible registers. For detailed information on instructions, see the ISA_C definition in the
ColdFire Family Programmer’s Reference Manual.
8.1.1
As with all ColdFire cores, the V1 ColdFire core is comprised of two separate pipelines decoupled by an
instruction buffer.
The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched
instruction stream is then gated into the two-stage operand execution pipeline (OEP), that decodes the
Freescale Semiconductor
Introduction
Overview
Instruction
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Execution
Operand
Pipeline
Pipeline
Fetch
DSOC
AGEX
IAG
IC
IB
Decode & Select,
Figure 8-1. V1 ColdFire Core Pipelines
Instruction Buffer
Operand Fetch
Generation,
Fetch Cycle
Instruction
Generation
Instruction
Address
Address
Execute
FIFO
®
processor core and an overview
Address [
Read Data[31:0]
Write Data[31:0]
23
:0]
8-1