MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 296

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16-Bit Serial Peripheral Interface (SPI16)
1
13-10
.
Note: PoR values of TNEAREF and RFIFOEF is 0. If status register is reset due to change of SPIMODE, FIFOMODE or SPE
than, if FIFOMODE = 1, TNEAREF and RFIFOEF resets to 1 else if FIFOMODE = 0, TNEAREF and RFIFOEF resets to 0
Reset
SPMF
SPRF
Field
7
6
W
R
SPRF
SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may
be read from the SPI data register (SPIxDH:SPIxDL). SPRF is cleared by reading SPRF while it is set, then
reading the SPI data register.
0 No data available in the receive data buffer.
1 Data available in the receive data buffer.
FIFOMODE=1
SPI Read FIFO FULL Flag — This bit indicates the status of the Read FIFO when FIFOMODE enabled. The
SPRF is set when the read FIFO has received 64bits (4 words or 8bytes) of data from the shifter and there has
been no CPU reads of SPIxDH:SPIxDL. SPRF is cleard by reading the SPI Data Register, which empties the
FIFO, assuming another SPI message is not received.
0 Read FIFO is not Full
1 Read FIFO is Full.
SPI Match Flag — SPMF is set after SPRF = 1 when the value in the receive data buffer matches the value in
SPIMH:SPIML. To clear the flag, read SPMF when it is set, then write a 1 to it.
0 Value in the receive data buffer does not match the value in SPIxMH:SPIxML registers.
1 Value in the receive data buffer matches the value in SPIxMH:SPIxML registers.
0
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
= Unimplemented or Reserved
SPMF
0
6
Table 13-8. SPIxS Register Field Descriptions
Figure 13-6. SPI Status Register (SPIxS)
SPTEF
1
5
MODF
0
4
Description
RNFULLF
3
0
TNEAREF
0
2
1
TXFULLF
Freescale Semiconductor
0
1
RFIFOEF
0
0
1