MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 622

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
26.4.3.1
The PST is 0x05 when a taken branch is executed. For some opcodes, a branch target address may be
loaded into the trace buffer (PSTB) depending on the CSR settings. CSR also controls the number of
address bytes loaded that is indicated by the PST marker value immediately preceding the DDATA entry
in the PSTB that begins the address entries.
26-58
0x0C–0x0F Indicates the number of address bytes to be loaded into the PST trace buffer. The capturing of branch
0x10–0x11 Reserved
PST[4:0]
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
Begin Execution of Taken Branch (PST = 0x05)
target addresses is controlled by CSR[BTB].
0x0C Reserved
0x0D Begin 2-byte address transfer on DDATA (Displayed address is shifted right 1: ADDR[16:1])
0x0E Begin 3-byte address transfer on DDATA (Displayed address is shifted right 1: ADDR[23:1])
0x0F Reserved
Completed execution of 2 sequential instructions
Completed execution of 3 sequential instructions
Completed execution of 4 sequential instructions
Completed execution of 5 sequential instructions
Completed execution of 6 sequential instructions
Completed execution of 7 sequential instructions
Completed execution of 8 sequential instructions
Completed execution of 9 sequential instructions
Completed execution of 10 sequential instructions
This value signals there has been a change in the breakpoint trigger state machine. It appears as a
single marker for each state change and is immediately followed by a DDATA value signaling the new
breakpoint trigger state encoding.
The DDATA breakpoint trigger state value is defined as (0x20 + 2 × CSR[BSTAT]):
0x20 No breakpoints enabled
0x22 Waiting for a level-1 breakpoint
0x24 Level-1 breakpoint triggered
0x2A Waiting for a level-2 breakpoint
0x2C Level-2 breakpoint triggered
Exception processing. This value signals the processor has encountered an exception condition.
Although this is a multi-cycle mode, there are only two PST = 0x1C values recorded before the mode
value is suppressed.
Emulator mode exception processing. This value signals the processor has encountered a debug
interrupt or a properly-configured trace exception. Although this is a multi-cycle mode, there are only
two PST = 0x1D values recorded before the mode value is suppressed.
Processor is stopped. This value signals the processor has executed a STOP instruction. Although this
is a multi-cycle mode because the ColdFire processor remains stopped until an interrupt or reset
occurs, there are only two PST = 0x1E values recorded before the mode value is suppressed
Processor is halted. This value signals the processor has been halted. Although this is a multi-cycle
mode because the ColdFire processor remains halted until a BDM go command is received or reset
occurs, there are only two PST = 0x1F values recorded before the mode value is suppressed
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 26-26. CF1 Debug Processor Status Encodings (continued)
Definition
Freescale Semiconductor
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