MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 359

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.4.4.2
To improve reliability and communication robustness, implementation of Packet Error Checking (PEC) by
SMBus devices is optional for SMBus devices but required for devices participating in and only during
the Address Resolution Protocol (ARP) process. The PEC is a CRC-8 error checking byte, calculated on
all the message bytes. The PEC is appended to the message by the device that supplied the last data byte.
If the PEC is present but not correct, a NACK is issued by receiver. Otherwise an ACK will be issued. In
order to calculate the CRC-8 by software, this module can hold SCL line to low after receiving eighth SCL
(bit 8th) if this byte is a data byte. So software can determine whether an ACK or NACK should be sent
out to the bus by setting or clearing TXAK bit if FASK (fast ACK/NACK enable bit) is enabled.
SMBus requires devices to acknowledge their own address always, as a mechanism to detect a removable
devices presence on the bus (battery, docking station, etc.) Besides to indicate a slave device busy
condition, SMBus is using the NACK mechanism also to indicate the reception of an invalid command or
data. Since such a condition may occur on the last byte of the transfer, it is required that SMBus devices
have the ability to generate the not acknowledge after the transfer of each byte and before the completion
of the transaction. This is important because SMBus does not provide any other resend signaling. This
difference in the use of the NACK signaling has implications on the specific implementation of the SMBus
port, especially in devices that handle critical system data such as the SMBus host and the SBS
components.
15.5
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
15.6
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine. The
user can determine the interrupt type by reading the status register. For SMBus timeouts interrupt, the
interrupt is driven by SLTF and masked with bit IICIE. The SLTF bit must be cleared by software by
writing a 1 to it in the interrupt routine. The user can determine the interrupt type by reading the status
register.
Freescale Semiconductor
Resets
Interrupts
FAST ACK and NACK
In the last byte of master receive slave transmit mode, the master should
send NACK to bus so FACK should be switched off before the last byte
transmit.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
NOTE
Table 15-16
occur, provided the IICIE bit
Inter-Integrated Circuit (IIC)
15-21