MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 466

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Analog-to-Digital Converter (S08ADC16)
21-10
ADICLK[1:0]
MODE[3:2]
ADIV[6:5]
ADLSMP
ADLPC
Field
6:5
3:2
1:0
7
4
Low-Power Configuration - ADLPC controls the power configuration of the successive approximation
converter. This optimizes power consumption when higher sample rates are not required.
0 Normal power configuration
1 Low-power configuration: The power is reduced at the expense of maximum clock speed.
Clock Divide Select - ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
Table 21-6
Sample Time Configuration - ADLSMP selects between different sample times based on the conversion mode
selected. This bit adjusts the sample period to allow higher impedance inputs to be accurately sampled or to
maximize conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall
power consumption when continuous conversions are enabled if high conversion rates are not required. When
ADLSMP=1, the Long Sample Time Select bits (ADLSTS[1:0]) can select the extent of the long sample time.
0 Short sample time
1 Long sample time (The ADLTS bits can select the extent of the long sample time)
Conversion Mode Selection - MODE bits are used to select between the ADC resolution mode. See
Input Clock Select - ADICLK bits select the input clock source to generate the internal clock ADCK. See
Table
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
21-8.
MODE
00
00
01
01
10
10
11
11
shows the available clock configurations.
Table 21-5. ADCCFG1 Register Field Descriptions
DIFFn
0
1
0
1
0
1
0
1
ADIV
00
01
10
11
Table 21-6. Clock Divide Select
Table 21-7. Conversion Modes
single-ended 8-bit conversion
Differential 9-bit conversion with 2s complement output
single-ended 12-bit conversion
Differential 13-bit conversion with 2s complement output
single-ended 10-bit conversion
Differential 11-bit conversion with 2s complement output
single-ended 16-bit conversion
Differential 16-bit conversion with 2s complement output
Divide Ratio
1
2
4
8
Conversion Mode Description
Description
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
Input clock
Clock Rate
Freescale Semiconductor
Table
21-7.