MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 183

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
Freescale Semiconductor
COPCLKS
These bits can be written only one time after reset. Subsequent writes are ignored.
Reset:
SOPT1[COPCLKS]
STOPE
WAITE
COPW
COPT
Field
3–2
7
6
5
4
1
0
W
R
N/A
0
0
0
1
1
1
Reserved, must be cleared.
RESERVED
Stop Mode Enable — This write-once bit is used to enable stop mode. If both stop and wait modes are disabled
and a user program attempts to execute a STOP instruction, an illegal opcode reset may be generated depending
on CPUCR[IRD].
WAIT Mode Enable — This write-anytime bit is used to enable WAIT mode. If both stop and wait modes are
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset may be generated
depending on CPUCR[IRD].
COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
SOPT1[COPCLKS] defines the COP timeout period as described in
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 1 kHz clock is source to COP.
1 Bus clock is source to COP.
COP Window Mode — This write-once bit specifies whether the COP operates in Normal or Window mode. In
Window mode, the 0x55–0xAA write sequence to the SRS register must occur within the last 25% of the selected
period; any write to the SRS register during the first 75% of the selected period resets the microcontroller.
0 Normal mode
1 Window mode
0
0
7
Control Bits
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
SOPT1[COPT]
0
0
6
Figure 7-6. System Options 1 (SOPT1) Register
00
01
10
11
01
10
11
Table 7-10. SOPT1 Bit Field Descriptions
Table 7-11. COP Configuration Details
STOPE
0
5
1
Clock Source
WAITE
1 kHz
1 kHz
1 kHz
Bus
Bus
Bus
N/A
1
4
Description
3
1
COP Window
(SOPT1[COPW] = 1)
COPT
196,608 cycles
49,152 cycles
6,144 cycles
Resets, Interrupts, and General System Control
Table
1
N/A
N/A
N/A
N/A
7-11.
1
2
1
Opens
COPCLKS
2
COP Overflow Count
10
2
2
0
1
8
5
COP is disabled
cycles (1,024 ms
cycles (256 ms
cycles (32 ms
2
2
2
13
16
18
1
cycles
cycles
cycles
COPW
0
0
2
1
7-17
)
)
1
1
)