MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 187

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.7.11
This register contains control bits to enable or disable the bus clock to the GPIO and KBI modules. Gating
off the clocks to unused peripherals is used to reduce the microcontroller’s run and wait currents. See
Section 7.6, “Peripheral Clock Gating,”
Freescale Semiconductor
Reset:
VREF
Field
Field
SPI3
SPI2
SPI1
KBI2
KBI1
LCD
PTF
IRQ
5
4
3
2
1
0
7
6
5
W
R
System Clock Gating Control 3 Register (SCGC3)
KBI2
VREF Clock Gate Control — This bit controls the bus clock gate to the VREF module.
0 Bus clock to VREF is disabled.
1 Bus clock to VREF is enabled.
IRQ Clock Gate Control — This bit controls the clock gate to the IRQ module.
0 Bus clock to theIRQ module is disabled.
1 Bus clock to the IRQ module isenabled.
LCD Clock Gate Control — This bit controls the clock gate to the LCD module.
0 Bus clock to the LCD module is disabled.
1 Bus clock to the LCD module is enabled.
SPI3 Clock Gate Control — This bit controls the bus clock gate to the SPI3 module.
0 Bus clock to the SPI3 module is disabled.
1 Bus clock to the SPI3 module is enabled.
SPI2 Clock Gate Control — This bit controls the bus clock gate to the SPI2 module.
0 Bus clock to the SPI2 module is disabled.
1 Bus clock to the SPI2 module is enabled.
SPI1 Clock Gate Control — This bit controls the bus clock gate to the SPI1 module.
0 Bus clock to the SPI1 module is disabled.
1 Bus clock to the SPI1 module is enabled.
KBI2 Clock Gate Control — This bit controls the bus clock gate to the KBI2 module.
0 Bus clock to the KBI2 module is disabled.
1 Bus clock to the KBI2 module is enabled.
KBI1 Clock Gate Control — This bit controls the bus clock gate to the KBI1 module.
0 Bus clock to the KBI1 module is disabled.
1 Bus clock to the KBI1 module is enabled.
PTF Clock Gate Control — This bit controls the clock gate to the PTF module.
0 Bus clock to the PTF module is disabled.
1 Bus clock to the PTF module is enabled.
1
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 7-12. System Clock Gating Control 3 Register (SCGC3)
KBI1
1
6
Table 7-16. SCGC2 Bit Field Descriptions
Table 7-17. SCGC3 Bit Field Descriptions
PTF
1
5
for more information.
PTE
1
4
Description
Description
PTD
3
1
Resets, Interrupts, and General System Control
PTC
1
2
PTB
1
1
PTA
1
0
7-21