MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 302

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16-Bit Serial Peripheral Interface (SPI16)
13.4
13.4.1
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1. While the SPE
bit is set, the four associated SPI port pins are dedicated to the SPI function as:
An SPI transfer is initiated in the master SPI device by reading the SPI status register (SPIxS) when
SPTEF = 1 and then writing data to the transmit data buffer (write to SPIxDH:SPIxDL). When a transfer
is complete, received data is moved into the receive data buffer. The SPIxDH:SPIxDL registers act as the
SPI receive data buffer for reads and as the SPI transmit data buffer for writes.
The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI Control Register 1
(SPIxC1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply
selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally
different protocols by sampling data on odd numbered SPSCK edges or on even numbered SPSCK edges.
13-16
TNEAREFCI
RNFULLFCI
SPTEFCI
RXFERR
TXFERR
SPRFCI
TXFOF
RXFOF
Field
•
•
•
•
7
6
5
4
3
2
1
0
Slave select (SS)
Serial clock (SPSCK)
Master out/slave in (MOSI)
Master in/slave out (MISO)
Functional Description
General
Transmit FIFO ErrorFlag- This flag indicates that TX FIFO error occured because entries in fifo goes above 8..
0 No TX Fifo Error Occured
1 TX Fifo error occured.
Receive FIFO Error Flag- This flag indicates that RX FIFO error occured because entries in fifo goes above 8.
0 No RX Fifo Error Occured
1 RX Fifo error occured.
TX FIFO Overflow Flag- This Flag indicates that TX FIFO overflow condition has occured..
0 TX FIFO overflow condition has not occured.
1 TX FIFO overflow condition occured.
RX FIFO Overflow Flag - This Flag indicates that RX FIFO overflow condition has occured..
0 RX FIFO overflow condition has not occured.
1 RX FIFO overflow condition occured.
Transmit FIFO Nearly Empty Flag Clear Interrupt Register - Write of 1 clears the TNEAREF interrupt provided
SPIxC3[3] is set.
Receive FIFO Nearly Full Flag Clear Interrupt Register - Write of 1 clears the RNFULLF interrupt provided
SPIxC3[3] is set.
Transmit FIFO Empty Flag Clear Interrupt Register - Write of 1 clears the SPTEF interrupt provided SPIxC3[3]
is set.
Receive FIFO Full Flag Clear Interrupt Register - Write of 1 clears the TNEAREF interrupt provided SPIxC3[3]
is set.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 13-10. SPIxCI Register Field Descriptions
Description
Freescale Semiconductor