MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 188

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Resets, Interrupts, and General System Control
7.7.12
This register contains control bits to enable or disable the bus clock to MTIM, Port Mux Control, TPM ,
CRC and PDB modules. Gating off the clocks to unused peripherals is used to reduce the microcontroller’s
run and wait currents. See
7-22
Reset:
Field
Field
CRC
TPM
PTE
PTD
PTC
PTB
PTA
PM
4
3
2
1
0
7
6
5
4
W
R
System Clock Gating Control 4 Register (SCGC4)
PTE Clock Gate Control — This bit controls the clock gate to the PTE module.
0 Bus clock to the PTE module is disabled.
1 Bus clock to the PTE module is enabled.
PTD Clock Gate Control — This bit controls the clock gate to the PTD module.
0 Bus clock to the PTD module is disabled.
1 Bus clock to the PTD module is enabled.
PTC Clock Gate Control — This bit controls the clock gate to the PTC module.
0 Bus clock to the PTC module is disabled.
1 Bus clock to the PTC module is enabled.
PTB Clock Gate Control — This bit controls the clock gate to the PTB module.
0 Bus clock to the PTB module is disabled.
1 Bus clock to the PTB module is enabled.
PTA Clock Gate Control — This bit controls the clock gate to the PTA module.
0 Bus clock to the PTA module is disabled.
1 Bus clock to the PTA module is enabled.
RESERVED
Port Mux Control — This bit controls the clock gate to the Port Mux Control module.
0 Bus clock to the Port Mux Control module is disabled.
1 Bus clock to the Port Mux Control module is enabled.
This bit can be set to zero once the mux controls have been programmed as desired. This bit affects
CRC — This bit controls the clock gate to the CRC module.
0 Bus clock to the CRC module is disabled.
1 Bus clock to the CRC module is enabled.
TPM Clock Gate Control — This bit controls the clock gate to the TPM module.
0 Bus clock to the TPM module is disabled.
1 Bus clock to the TPM module is enabled.
1
1
7
programming of the mux controls only. The actual data paths to/from pins are unaffected.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 7-13. System Clock Gating Control 3 Register (SCGC4)
PM
1
6
Section 7.6, “Peripheral Clock Gating,”
Table 7-17. SCGC3 Bit Field Descriptions
Table 7-18. SCGC4 Bit Field Descriptions
CRC
1
5
TPM
1
4
Description
Description
PDB
3
1
for more information.
MTIM3
1
2
Freescale Semiconductor
MTIM2
1
1
MTIM1
1
0