MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 612

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
monitoring as the execution of this command is considerably less obtrusive to the real-time operation of
an application than a BACKGROUND/read-PC/GO command sequence.
26.4.1.5.18 WRITE_CREG
If the processor is halted, this command writes the 32-bit operand to the selected control register. This
register grouping includes the PC, SR, CPUCR, MACSR, MASK, ACC, VBR, and OTHER_A7. Accesses
to processor control registers are always 32-bits wide, regardless of implemented register width. The
register is addressed through the core register number (CRN). See
CRG is 11.
If the processor is not halted, this command is rejected as an illegal operation and no operation is
performed.
26.4.1.5.19 WRITE_DREG
This command writes the 32-bit operand to the selected debug control register. This grouping includes all
the debug control registers ({X}CSRn, BAAR, AATR, TDR, PBRn, PBMR, ABxR, DBR, DBMR).
Accesses to debug control registers are always 32-bits wide, regardless of implemented register width. The
register is addressed through the core register number (CRN). See
26-48
When writing XCSR, CSR2, or CSR3, WRITE_DREG only writes
bits 23–0. The upper byte of these debug registers is only written with the
special WRITE_XCSR_BYTE, WRITE_CSR2_BYTE, and
WRITE_CSR3_BYTE commands.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Write CPU control register
Write debug control register
0xC0+CRN
0x80+CRN
host →
host →
target
target
CREG data
DREG data
[31–24]
[31–24]
host →
host →
target
target
CREG data
DREG data
NOTE
[23–16]
[23–16]
host →
host →
target
target
CREG data
DREG data
host →
host →
[15–8]
[15–8]
target
target
Table 26-24
Table 26-4
Active Background
DREG data
CREG data
host →
host →
target
target
Non-intrusive
[7–0]
[7–0]
for CRN details.
for the CRN details when
D
Y
D
Y
L
L
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