MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 226

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Multiply-Accumulate Unit (MAC)
Table 9-3
9.2.2
The MASK register performs a simple AND with the operand address for MAC instructions. The
processor calculates the normal operand address and, if enabled, that address is then ANDed with
{0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand
address can be constrained to a certain memory region. This is used primarily to implement circular queues
with the (An)+ addressing mode.
This minimizes the addressing support required for filtering, convolution, or any routine that implements
a data array as a circular queue. For MAC + MOVE operations, the MASK contents can optionally be
included in all memory effective address calculations. The syntax is as follows:
The & operator enables the MASK use and causes bit 5 of the extension word to be set. The exact
algorithm for the use of MASK is:
9-4
Field
mac.sz
V
1
0
summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.
Mask Register (MASK)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 1.11
Ry,RxSF,<ea>y&,Rw
Overflow. Set if an arithmetic overflow occurs, implying that the result cannot be represented in the operand
size. After set, V remains set until the accumulator register is loaded with a new value or MACSR is directly
loaded. MULS and MULU instructions do not change this value.
Carry. This field is always zero.
S/U
Table 9-3. Summary of S/U, F/I, and R/T Control Bits
0
0
0
1
1
1
Table 9-2. MACSR Field Descriptions (continued)
F/I
0
1
1
0
1
1
R/T
0
1
0
1
x
x
Signed, integer
Signed, fractional
Truncate on MAC.L and MSAC.L
No round on accumulator stores
Signed, fractional
Round on MAC.L and MSAC.L
No round on accumulator stores
Unsigned, integer
Signed, fractional
Truncate on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
Signed, fractional
Round on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
Operational Modes
Description
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