MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 124

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.5.2.3
4.6
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
4-14
Reset:
KBEDGn
Field
•
•
7–0
W
R
Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as
before the STOP instruction was executed (port states are lost and need to be restored upon exiting
stop2). CPU register status and the state of I/O registers should be saved in RAM before the
executing the STOP instruction to place the MCU in stop2 mode.
After recovery from stop2 mode, before accessing any I/O, examine the state of the
SPMSC2[PPDF] bit.
— If the PPDF bit is cleared, I/O must be initialized as if a power-on-reset had occurred.
— If the PPDF bit is set, I/O register states should be restored from the values saved in RAM
Then write a 1 to the SPMSC2[PPDACK] bit. Access to I/O is now permitted again in the user
application program.
In stop3 and stop4 modes, all I/O is maintained because internal logic circuity stays powered. After
recovery, normal I/O function is available to the user.
Pin Behavior in Stop Modes
KBEDG7
before the STOP instruction was executed and peripherals may require initialization or
restoration to their pre-stop condition.
KBIx Edge Selects — Each of the KBEDGn bits serves a dual purpose by selecting the polarity of the active
interrupt edge as well as selecting a pullup or pulldown device if enabled.
0 A pullup device is connected to the associated pin and detects falling edge/low level for interrupt generation.
1 A pulldown device is connected to the associated pin and detects rising edge/high level for interrupt
KBIx Interrupt Edge Select Register (KBIxES)
0
7
generation.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
KBEDG6
0
6
Figure 4-15. KBIx Edge Select Register (KBIxES)
Table 4-20. KBIxES Field Descriptions
KBEDG5
0
5
KBEDG4
0
4
Description
KBEDG3
3
0
KBEDG2
0
2
KBEDG1
Freescale Semiconductor
0
1
KBEDG0
0
0