MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 201

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.3
8.3.1
The original ColdFire instruction set architecture (ISA_A) was derived from the M68000 family opcodes
based on extensive analysis of embedded application code. The ISA was optimized for code compiled
from high-level languages where the dominant operand size was the 32-bit integer declaration. This
approach minimized processor complexity and cost, while providing excellent performance for compiled
applications.
After the initial ColdFire compilers were created, developers noted there were certain ISA additions that
would enhance code density and overall performance. Additionally, as users implemented ColdFire-based
designs into a wide range of embedded systems, they found certain frequently-used instruction sequences
that could be improved by the creation of additional instructions.
The original ISA definition minimized support for instructions referencing byte- and word-sized operands.
Full support for the move byte and move word instructions was provided, but the only other opcodes
supporting these data types are CLR (clear) and TST (test). A set of instruction enhancements has been
Freescale Semiconductor
Field
10–8
CCR
7–0
Reset
BDM: Load: 0xEE (SR)
15
14
13
12
11
M
T
S
I
W
R
Store: 0xCE (SR)
Trace enable. When set, the processor performs a trace exception after every instruction.
Reserved, must be cleared.
Supervisor/user state.
0 User mode
1 Supervisor mode
Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or
move to SR instructions.
Reserved, must be cleared.
Interrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or
equal to current level, except edge-sensitive level 7 requests, which cannot be masked.
Refer to
Functional Description
15
T
0
Instruction Set Architecture (ISA_C)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
14
Section 8.2.4, “Condition Code Register
0
0
13
S
1
System Byte
12
M
0
11
0
0
Table 8-4. SR Field Descriptions
Figure 8-9. Status Register (SR)
10
1
1
9
I
(CCR)”.
Description
1
8
0
0
7
0
0
6
Condition Code Register (CCR)
0
0
5
—
X
4
Access: Supervisor read/write
—
N
3
—
Z
2
BDM read/write
ColdFire Core
—
V
1
—
C
0
8-9