HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 12

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3.6
Section 4 Clock Pulse Generator .......................................................................53
4.1
4.2
4.3
Section 5 Exception Processing.........................................................................61
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Rev.4.00 Mar. 27, 2008 Page x of xliv
REJ09B0108-0400
Note on Changing Operating Mode .................................................................................. 52
Oscillator........................................................................................................................... 55
4.1.1
4.1.2
Function for Detecting Oscillator Halt.............................................................................. 57
Usage Notes ...................................................................................................................... 58
4.3.1
4.3.2
Overview........................................................................................................................... 61
5.1.1
5.1.2
5.1.3
Resets ................................................................................................................................ 65
5.2.1
5.2.2
5.2.3
Address Errors .................................................................................................................. 67
5.3.1
5.3.2
Interrupts........................................................................................................................... 69
5.4.1
5.4.2
5.4.3
Exceptions Triggered by Instructions ............................................................................... 71
5.5.1
5.5.2
5.5.3
5.5.4
Cases when Exception Sources Are not Accepted............................................................ 73
5.6.1
5.6.2
Stack Status after Exception Processing Ends .................................................................. 74
Usage Notes ...................................................................................................................... 75
5.8.1
5.8.2
5.8.3
Connecting Crystal Resonator ............................................................................. 55
External Clock Input Method............................................................................... 56
Note on Crystal Resonator ................................................................................... 58
Notes on Board Design ........................................................................................ 58
Types of Exception Processing and Priority ........................................................ 61
Exception Processing Operations......................................................................... 62
Exception Processing Vector Table ..................................................................... 63
Types of Reset ..................................................................................................... 65
Power-On Reset ................................................................................................... 65
Manual Reset ....................................................................................................... 66
Cause of Address Error Exception....................................................................... 67
Address Error Exception Processing.................................................................... 68
Interrupt Sources.................................................................................................. 69
Interrupt Priority Level ........................................................................................ 70
Interrupt Exception Processing ............................................................................ 70
Types of Exceptions Triggered by Instructions ................................................... 71
Trap Instructions .................................................................................................. 71
Illegal Slot Instructions ........................................................................................ 72
General Illegal Instructions.................................................................................. 72
Immediately after Delayed Branch Instruction .................................................... 73
Immediately after Interrupt-Disabled Instruction ................................................ 73
Value of Stack Pointer (SP) ................................................................................. 75
Value of Vector Base Register (VBR) ................................................................. 75
Address Errors Caused by Stacking of Address Error Exception Processing...... 75