HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 72

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2. CPU
Rev.4.00 Mar. 27, 2008 Page 26 of 882
REJ09B0108-0400
Addressing
Mode
Indirect register
addressing with
displacement
Indirect indexed
register
addressing
Indirect GBR
addressing with
displacement
Indirect indexed
GBR
addressing
Instruction
Format
@(disp:4,
Rn)
@(R0, Rn) The effective address is the sum of Rn and R0.
@(disp:8,
GBR)
@(R0,
GBR)
Effective Address Calculation
The effective address is the sum of Rn and a 4-bit
displacement (disp). The value of disp is zero-
extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
The effective address is the sum of GBR value and
an 8-bit displacement (disp). The value of disp is
zero-extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
The effective address is the sum of GBR value and
R0.
(zero-extended)
(zero-extended)
GBR
1/2/4
Rn
R0
R0
GBR
1/2/4
disp
disp
Rn
×
×
+
+
+
+
Rn + disp × 1/2/4
GBR + R0
+ disp × 1/2/4
Rn + R0
GBR
Equation
Byte:
Rn + disp
Word:
Rn + disp × 2
Longword:
Rn + disp × 4
Rn + R0
Byte:
GBR + disp
Word:
GBR + disp × 2
Longword:
GBR + disp × 4
GBR + R0