HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 203
HD6417144F50V
Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD6417144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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9.6.3
Idle cycles can be inserted to prevent extension of the RD or WRxx signal assert period beyond
the length of the CSn signal assert period by setting the SW3 to SW0 bits of BCR2. This allows
for flexible interfaces with external circuitry. The timing is shown in figure 9.6. Th and Tf cycles
are added respectively before and after the normal cycle. Only CSn is asserted in these cycles; RD
and WRxx signals are not. Further, data is extended up to the Tf cycle, which is effective for gate
arrays and the like, which have slower write operations.
CS Assert Period Extension
Read
Write
Figure 9.6 CS Assert Period Extension Function
Address
DACK
WRxx
Data
Data
CSn
RD
CK
Th
T1
T2
Rev.4.00 Mar. 27, 2008 Page 157 of 882
Tf
9. Bus State Controller (BSC)
REJ09B0108-0400
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