HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 591

IC SUPERH MCU ROMLESS 112QFP

HD6417144F50V

Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet

Specifications of HD6417144F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.3.2
ADCSR for each module controls A/D conversion operations.
Bit
7
6
5
4
3
2
Bit Name Initial Value
ADF
ADIE
ADM
A/D Control/Status Register_0, 1 (ADCSR_0, ADCSR_1)
0
0
0
0
1
0
R/W
R/(W)*
R/W
R
R/W
R
R
Description
A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
[Clearing conditions]
A/D Interrupt Enable
The A/D conversion end interrupt (ADI) request is
enabled when 1 is set
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
Reserved
This bit is always read as 0. The write value should
always be 0.
A/D Operating Mode Select
Selects the A/D conversion mode.
0: Single mode
1: Scan mode
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
Reserved
This bit is always read as 1. The write value should
always be 1.
Reserved
This bit is always read as 0. The write value should
always be 0.
When A/D conversion ends in single mode
When A/D conversion ends on all specified
channels in scan mode
When 0 is written after reading ADF = 1
When the DMAC or the DTC is activated by an
ADI interrupt and data is read from ADDR while
the DTMR bit in the DTC is cleared to 0
Rev.4.00 Mar. 27, 2008 Page 545 of 882
15. A/D Converter
REJ09B0108-0400

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