HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 490

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13. Serial Communication Interface (SCI)
13.6.2
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in a sample flowchart in figure 13.15. When the operating mode,
transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the
change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and
ORER flags, or the contents of RDR.
Rev.4.00 Mar. 27, 2008 Page 444 of 882
REJ09B0108-0400
Note: * In simultaneous transmit and receive operations, the TE and RE bits should both
Set CKE1 and CKE0 bits in SCR
Set PFC of the external pin used
Set TE and RE bits in SCR to 1
SCI Initialization (Clocked Synchronous Mode)
Clear RIE, TIE, TEIE, MPIE,
TE and RE bits in SCR to 0 *
Set RIE, TIE, and TEIE bits
Set data transfer format in
(TE and RE bits are 0)
1-bit interval elapsed?
be cleared to 0 or set to 1 simultaneously.
Set value in BRR
Start initialization
<Transfer start>
SCK, TxD, RxD
SMR
Figure 13.15 Sample SCI Initialization Flowchart
Yes
Wait
No
[4]
[5]
[2]
[3]
[1]
[1] Set the clock selection in SCR.
[2] Set the data transfer format in SMR.
[3] Write a value corresponding to the bit
[4] Set PFC of the external pin used. Set
[5] Wait at least one bit interval, then set
rate to BRR. Not necessary if an
external clock is used.
RxD input during receiving and TxD
output during transmitting. Set SCK
input/output according to contents set
by CKE1 and CKE0.
the TE bit or RE bit in SCR to 1. * At this
time, the TxD, RxD, and SCK pins can
be used. The TxD pin is in a mark state
during transmitting. When synchronous
clock output (clock master) is set during
receiving in synchronous mode,
outputting clocks from the SCK pin
starts.