HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 532

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14. I
14.3.6
ICSR includes flags that indicate bus states. See also table 14.4 and table 14.5.
Rev.4.00 Mar. 27, 2008 Page 486 of 882
REJ09B0108-0400
Bit
7
6
5
2
C Bus Interface (IIC) Option
Bit Name Initial Value R/W
ESTP
STOP
IRTR
I
2
C Bus Status Register (ICSR)
0
0
0
R/(W)* Erroneous Stop Condition Detection Flag
R/(W)* Normal Stop Condition Detection Flag
R/(W)* I
Description
This bit is enabled in the I
[Setting condition]
•
[Clearing conditions]
•
•
This bit is enabled in the I
[Setting condition]
•
[Clearing conditions]
•
•
Flag
The IRTR flag indicates that the I
generated an interrupt for the CPU at the end of
transmission and reception one frame of data. The IRIC
flag is set to 1 at the same time as the IRTR flag is set to 1.
[Setting conditions]
•
•
[Clearing conditions]
•
•
2
C Bus Interface Continuous Transfer Interrupt Request
Detection of the stop condition during the transfer of
one frame
Writing of 0 to this bit after reading ESTP = 1
Clearing of the IRIC flag to 0
Detection of the stop condition after the transfer of one
frame
Writing of 0 to this bit after reading STOP = 1
Clearing of the IRIC flag to 0
Setting of the ICDRE or ICDRF flag to 1 while AASX is
1 in the I
Setting of the ICDRE or ICDRF flag to 1, when in
master mode in I2C bus interface or synchronous serial
format
Writing of 0 to this bit after reading IRTR = 1
Clearing of the IRIC flag to 0 with ICE = 0
2
C bus interface in the slave mode.
2
2
C bus format in the slave mode.
C bus format in the slave mode.
2
C bus interface has