HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 162

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8. Data Transfer Controller (DTC)
8.2.1
DTMR is a 16-bit register that selects the DTC operating mode.
Rev.4.00 Mar. 27, 2008 Page 116 of 882
REJ09B0108-0400
Bit
15
14
13
12
11
10
9
8
Bit Name
SM1
SM0
DM1
DM0
MD1
MD0
Sz1
Sz0
DTC Mode Register (DTMR)
Initial Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
—
—
—
—
—
—
—
—
Description
Source Address Mode 1 and 0
These bits specify a DTSAR operation after a data
transfer.
0x: DTSAR is fixed
10: DTSAR is incremented after a transfer
11: DTSAR is decremented after a transfer
Destination Address Mode 1 and 0
These bits specify a DTDAR operation after a data
transfer.
0x: DTDAR is fixed
10: DTDAR is incremented after a transfer
11: DTDAR is decremented after a transfer
DTC Mode 1 and 0
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
DTC Data Transfer Size 1 and 0
Specify the size of data to be transferred.
00: Byte-size transfer
01: Word-size transfer
10: longword-size transfer
11: Setting prohibited
(by +1 when Sz 1 and 0 = 00; by +2 when Sz 1
and 0 = 01; by +4 when Sz 1 and 0 = 10)
(by –1 when Sz 1 and 0 = 00; by –2 when Sz 1
and 0 = 01; by –4 when Sz 1 and 0 = 10)
(by +1 when Sz 1 and 0 = 00; by +2 when Sz 1
and 0 = 01; by +4 when Sz 1 and 0 = 10)
(by –1 when Sz 1 and 0 = 00; by –2 when Sz 1
and 0 = 01; by –4 when Sz 1 and 0 = 10)