HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 172

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8. Data Transfer Controller (DTC)
The 32-bit DTSAR designates the DTC transfer source address and the 32-bit DTDAR designates
the transfer destination address. After each transfer, DTSAR and DTDAR are independently
incremented, decremented, or left fixed depending on its register information.
Rev.4.00 Mar. 27, 2008 Page 126 of 882
REJ09B0108-0400
DTCRA = DTCRA – 1 (normal/block transfer mode)
DTCRAL = DTCRAL – 1 (repeat mode)
DTSAR, DTDAR update
DTCRB = DTCRB – 1 (block transfer mode)
When DISEL = 1 or DTCRA = 0 (normal/block transfer mode)
When DISEL = 1 (repeat transfer mode)
DTMR, DTCR, DTIAR, DTSAR, DTDAR
Transfer information write
Transfer information read
Transfer (1 transfer unit)
Figure 8.5 DTC Operation Flowchart
NMI or address error
DTC vector read
NMIF = AE = 0?
Transfer request
Initial settings
NMIF • NMIM
generated?
+ AE = 1?
Start
End
CPU interrupt request
Yes
Yes
Yes
No
No
No
Transfer information write
transfer mode and
DTCRB ≠ 0?
CHNE = 0?
Block
No
Yes
Yes
No