HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 538
HD6417144F50V
Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD6417144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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14. I
14.3.8
The ICDRE flag is set and cleared under the conditions as shown below. Since the ICDRE flag is
an internal flag, it cannot be accessed.
Rev.4.00 Mar. 27, 2008 Page 492 of 882
REJ09B0108-0400
Bit Name
ICDRE
2
C Bus Interface (IIC) Option
ICDRE Flag (Internal Flag)
0
Initial Value
Description
Transmit Data Write Request Flag
This flag is an internal flag that indicates the ICDR (ICDRT) state in
transmission mode.
0: Indicates that the data to be transmitted has been already written to
1: Indicates that data has been transferred from ICDRT to ICDRS and
[Setting conditions]
•
•
[Clearing conditions]
•
•
•
Note that if the ACKE bit is set to 1 in I
acknowledge bit decision, ICDRE is not set when data transmission is
completed while the acknowledge bit is 1.
Due to the set condition B above, ICDRE is temporarily cleared to 0
when data is written to ICDR (ICDRT); however, since data is
transferred from ICDRT to ICDRS immediately, ICDRE is set to 1
again. Do not write data to ICDR when TRS = 0 because the ICDRE
flag value is invalid during the time.
ICDR (ICDRT) or ICDR is initialized.
is being transmitted, or the start condition has been detected or
transmission has been completed, thus allowing the next data to be
written to.
When the start condition is detected from the bus line state in I
bus format or serial format.
When data is transferred from ICDRT to ICDRS.
A. When data transmission is completed while ICDRE =0 (at the
B. When ICDR is written to in transmit mode after data
When transmit data is written to ICDR (ICDRT).
When the stop condition is detected in I
format.
When 0 is written to the ICE bit.
rising edge of the 9th cycle of the clock).
transmission is completed while ICDRE = 1.
2
C bus format thus enabling
2
C bus format or serial
2
C
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