HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 156

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7. User Break Controller (UBC)
Break on CPU Data Access Cycle
1. Register settings: UBARH = H'0012
2. Register settings: UBARH = H'00A8
Break on DMAC/DTC Cycle
1. Register settings: UBARH = H'0076
2. Register settings: UBARH = H'0023
Rev.4.00 Mar. 27, 2008 Page 110 of 882
REJ09B0108-0400
Conditions set:
A user break interrupt occurs when word data is written into address H'00123456.
Conditions set:
A user break interrupt does not occur because the word access was performed on an even
address.
Conditions set:
A user break interrupt occurs when longword data is read from address H'0076BCDC.
Conditions set:
A user break interrupt does not occur because no instruction fetch is performed in the
DMAC/DTC cycle.
Address: H'00123456
Address: H'00A80391
Address: H'002345C8
UBARL = H'3456
UBBR = H'006A
UBCR = H'0000
Bus cycle: CPU, data access, write, word
Interrupt requests enabled
UBARL = H'0391
UBBR = H'0066
UBCR = H'0000
Bus cycle: CPU, data access, read, word
Interrupt requests enabled
UBARL = H'BCDC
UBBR = H'00A7
UBCR = H'0000
Address: H'0076BCDC
Bus cycle: DMAC/DTC, data access, read, longword
Interrupt requests enabled
UBARL = H'45C8
UBBR = H'0094
UBCR = H'0000
Bus cycle: DMAC/DTC, instruction fetch, read
(operand size is not included in conditions)
Interrupt requests enabled