HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 28

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 8.5 DTC Operation Flowchart......................................................................................... 126
Figure 8.6 Memory Mapping in Normal Mode .......................................................................... 127
Figure 8.7 Memory Mapping in Repeat Mode ........................................................................... 128
Figure 8.8 Memory Mapping in Block Transfer Mode............................................................... 130
Figure 8.9 Chain Transfer........................................................................................................... 131
Figure 8.10 DTC Operation Timing Example (Normal Mode) .................................................. 132
Section 9 Bus State Controller (BSC)
Figure 9.1 BSC Block Diagram.................................................................................................. 138
Figure 9.2 Address Format ......................................................................................................... 141
Figure 9.3 Basic Timing of External Space Access.................................................................... 154
Figure 9.4 Wait State Timing of External Space Access (Software Wait Only) ........................ 155
Figure 9.5 Wait State Timing of External Space Access
Figure 9.6 CS Assert Period Extension Function ....................................................................... 157
Figure 9.7 Example of Idle Cycle Insertion................................................................................ 159
Figure 9.8 Example of Idle Cycle Insertion at Same Space Consecutive Access....................... 160
Figure 9.9 Bus Mastership Release Procedure............................................................................ 162
Figure 9.10 Example of 8-bit Data Bus Width ROM Connection .............................................. 163
Figure 9.11 Example of 16-bit Data Bus Width ROM Connection ............................................ 163
Figure 9.12 Example of 32-bit Data Bus Width ROM Connection (only for SH7145).............. 164
Figure 9.13 Example of 8-bit Data Bus Width SRAM Connection............................................ 164
Figure 9.14 Example of 16-bit Data Bus Width SRAM Connection.......................................... 165
Figure 9.15 Example of 32-bit Data Bus Width SRAM Connection (only for SH7145)............ 165
Figure 9.16 One Bus Cycle......................................................................................................... 166
Section 10 Direct Memory Access Controller (DMAC)
Figure 10.1 DMAC Block Diagram............................................................................................ 168
Figure 10.2 DMAC Transfer Flowchart ..................................................................................... 181
Figure 10.3 (1) Round Robin Mode............................................................................................ 185
Figure 10.3 (2) Example of Changes in Priority in Round Robin Mode .................................... 186
Figure 10.4 Data Flow in Single Address Mode......................................................................... 188
Figure 10.5 Example of DMA Transfer Timing in Single Address Mode.................................. 189
Figure 10.6 Direct Address Operation during Dual Address Mode............................................ 190
Figure 10.7 Example of Direct Address Transfer Timing in Dual Address Mode ..................... 191
Figure 10.8 Dual Address Mode and Indirect Address Operation
Figure 10.9 Dual Address Mode and Indirect Address Transfer Timing Example
Figure 10.10 Dual Address Mode and Indirect Address Transfer Timing Example
Rev.4.00 Mar. 27, 2008 Page xxvi of xliv
REJ09B0108-0400
(Two Software Wait States + WAIT Signal Wait State)........................................... 156
(When External Memory Space Is 16 Bits)............................................................. 192
(External Memory Space to External Memory Space, 16-Bit Width)..................... 193
(On-chip Memory Space to On-chip Memory Space)........................................... 194