HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 446

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 400 of 882
REJ09B0108-0400
Bit
4
3
2
1
0
Bit Name
O/E
STOP
MP
CKS1
CKS0
0
0
Initial Value
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
When even parity is set, parity bit addition is
performed in transmission so that the total number of
1 bits in the transmit character plus the parity bit is
even. In reception, a check is performed to see if the
total number of 1 bits in the receive character plus
parity bit is even.
Description
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
When odd parity is set, parity bit addition is
performed in transmission so that the total number of
1 bits in the transmit character plus the parity bit is
odd. In reception, a check is performed to see if the
total number of 1 bits in the receive character plus
the parity bit is odd.
Stop Bit Length (enabled only in asynchronous
mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the
next transmit character.
Multiprocessor Mode (enabled only in asynchronous
mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and
O/E bit settings are invalid in multiprocessor mode.
Clock Select 1 and 0
These bits select the clock source for the baud rate
generator.
00: Pφ clock (n = 0)
01: Pφ/8 clock (n = 1)
10: Pφ/32 clock (n = 2)
11: Pφ/128 clock (n = 3)
For the relation between the setting of CKS1 and
CKS2 and the baud rate, see section 13.3.9, Bit Rate
Register (BRR). n is the decimal display of the value
of n in BRR (see section 13.3.9, Bit Rate Register
(BRR)).