HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 560

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14. I
Continuous Receive Operation:
Figure 14.20 is a flowchart that gives an example of operations in slave receive mode (HNDS =
0).
Rev.4.00 Mar. 27, 2008 Page 514 of 882
REJ09B0108-0400
Figure 14.20 Example: Flowchart of Operations in Slave Transmit Mode (HNDS = 0)
2
C Bus Interface (IIC) Option
Read AASX, AAS, and ADZ flags in ICSR
No
No
Read the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Set MST = 0 and TRS = 0
Read the TRS bit in ICCR
Set HNDS = 0 (SCRX)
Set ACKB = 0 (ICSR)
Set ACKB = 1 (ICSR)
Wait for one frame
Receive (n -2)th
or STOP = 1?
and ADZ =1?
Initial setting
ICDRF = 1?
ICDRF = 1?
ICDRF = 1?
Read ICDR
Read ICDR
Read ICDR
IRIC = 1?
IRIC = 1?
TRS = 1?
ESTP = 1
AAS = 1
(ICCR)
byte?
Start
End
Yes
No
Yes
Yes
No
No
Yes
Yes
Yes
No
Yes
Yes
No
No
No
Yes
[1] Initial setting. Set slave receive mode.
[2] Read remained receive data.
[3] to [7] Wait for one byte to be received (slave address + R/W)
[8] Clear the IRIC flag.
[9] Wait for ACKB setting and set acknowledge data for the final reception
[10] Read receive data. The first read is a dummy read.
[11] Wait for one byte to be received
[12] Stop condition is detected
[13] Clear the IRIC flag.
[14] Read final receive data.
[15] Clear the IRIC flag.
General call address processing
Slave transmit mode
(IRIC is set at the 9th cycle of the clock).
(after the rise of the 9th cycle of (n-1)th byte data).
(IRIC is set at the 9 th cycle of the clock)
* n: Address + all receive byte
* Description omitted