HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 556
HD6417144F50V
Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD6417144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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14. I
Rev.4.00 Mar. 27, 2008 Page 510 of 882
REJ09B0108-0400
Figure 14.17 Example: Flowchart of Operations in the Slave Receive Mode (HNDS = 1)
2
C Bus Interface (IIC) Option
Read AASX, AAS, and ADZ flags in ICSR
Set MST = 0 and TRS = 0 (ICCR)
No
No
No
Read the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
Read ICDR and clear IRIC
Read the TRS bit in ICCR
and HNDS = 1 (SCRX)
Set ACKB = 0 (ICSR)
Set ACKB = 1 (ICSR)
Final reception?
Set initial value
and ADZ = 1?
ICDRF = 1?
Read ICDR
Read ICDR
IRIC = 1?
IRIC = 1?
TRS = 1?
IRIC = 1?
AAS = 1
Start
End
Yes
Yes
Yes
Yes
No
No
No
Yes
No
Yes
Yes
[1] Initial setting. Set slave receive mode.
[2] Read remained receive data.
[3] to [7] Wait for one byte to be received (slave address + R/W).
[8] Clear the IRIC flag.
[10] Read receive data. The first read is a dummy read.
[5] to [7] Wait for completion of reception.
[8] Clear the IRIC flag.
[9] Set acknowledge data for the final reception.
[10] Read receive data.
[11] Detect stop condition.
[12] Clear the IRIC flag.
General call address processing
Slave transmit mode
* Description omitted
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