HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 133
HD6417144F50V
Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD6417144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.4
There are five types of interrupt sources: NMI, user breaks, H-UDI, IRQ, and on-chip peripheral
modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and
16 the highest). Giving an interrupt a priority level of 0 masks it.
6.4.1
NMI Interrupts: The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin
is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register 1 (ICR1)
to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt
mask level bits (I3 to I0) in the status register (SR) to level 15.
IRQ Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ7. Set the IRQ
sense select bits (IRQ0S to IRQ7S) of the interrupt control register 1 (ICR1) and IRQ edge select
bit (IRQ0ES[1:0] to IRQ7ES[1:0]) of the interrupt control register 2 (ICR2) to select low level
detection, falling edge detection, or rising edge detection for each pin. The priority level can be set
from 0 to 15 for each pin using the interrupt priority registers A and B (IPRA and IPRB).
When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC
during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when
the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ
flags (IRQ0F to IRQ7F) of the IRQ status register (ISR).
When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the
INTC upon detecting a change on the IRQ pin from high to low level. The results of detection for
IRQ interrupt request are maintained until the interrupt request is accepted. It is possible to
confirm that IRQ interrupt requests have been detected by reading the IRQ flags (IRQ0F to
IRQ7F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request
detection results can be cleared
In IRQ interrupt exception processing, the interrupt mask bits (I3 to I0) of the status register (SR)
are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block
diagram of this IRQ7 to IRQ0 interrupts.
Interrupt Sources
External Interrupts
Rev.4.00 Mar. 27, 2008 Page 87 of 882
6. Interrupt Controller (INTC)
REJ09B0108-0400
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