HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 547

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2
14. I
C Bus Interface (IIC) Option
14.4.4
Operations in Master Reception
In master receive mode, the master device outputs the receive clock, receives data, and returns
acknowledgements of reception. The slave device transmits the data.
The master device transmits data of the slave address + R/W (1: Read) in the first frame after start
condition issuance in master transmit mode. After the slave device is selected, operation is
changed to reception.
Reception with HNDS Function (HNDS = 1):
Figure 14.10 is a flowchart that gives an example of operations in master receive mode (HNDS =
1).
Rev.4.00 Mar. 27, 2008 Page 501 of 882
REJ09B0108-0400