HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 57
![IC SUPERH MCU ROMLESS 112QFP](/photos/12/40/124045/hd6417144f50v_sml.jpg)
HD6417144F50V
Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD6417144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 57 of 932
- Download datasheet (6Mb)
Type
Multifunction
timer-pulse
unit (MTU)
Serial
communication
interface (SCI)
I
interface
(option)
2
C bus
Symbol
TCLKA to
TCLKD
TIOC0A to
TIOC0D
TIOC1A,
TIOC1B
TIOC2A,
TIOC2B
TIOC3A to
TIOC3D
TIOC4A to
TIOC4D
TXD3 to
TXD0
RXD3 to
RXD0
SCK3 to
SCK0
SCL0
SDA0
I/O
Input
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Output
Input
Input/
Output
Input/
Output
Input/
Output
Name
External clock
input for MTU
timer
MTU input
capture/output
compare
(channel 0)
MTU input
capture/output
compare
(channel 1)
MTU input
capture/output
compare
(channel 2)
MTU input
capture/output
compare
(channel 3)
MTU input
capture/output
compare
(channel 4)
Transmitted
data
Received data Data input pins.
Serial clock
I
input/ output
I
input/ output
2
2
C clock
C data
Function
These pins input an external clock.
The TGRA_0 to TGRD_0 input capture
input/output compare output/PWM output
pins.
The TGRA_1 to TGRB_1 input capture
input/output compare output/PWM output
pins.
The TGRA_2 to TGRB_2 input capture
input/output compare output/PWM output
pins.
The TGRA_3 to TGRD_3 input capture
input/output compare output/PWM output
pins.
The TGRA_4 to TGRB_4 input capture
input/output compare output/PWM output
pins.
Data output pins.
Clock input/output pins.
I
a bus.
Output a clock in the NMOS open-drain
method.
I
a bus.
Output data in the NMOS open-drain
method.
2
2
C bus clock input/output pins, which drive
C bus data input/output pins, which drive
Rev.4.00 Mar. 27, 2008 Page 11 of 882
REJ09B0108-0400
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