HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 157
HD6417144F50V
Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD6417144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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7.5
7.5.1
Two instructions may be simultaneously fetched in instruction fetch operation. Once a break
condition is set on the latter of these two instructions, a user break interrupt will occur before the
latter instruction, even though the contents of the UBC registers are modified to change the break
conditions immediately after the fetching of the former instruction.
7.5.2
When a conditional branch instruction or TRAPA instruction causes a branch, the order of
instruction fetching and execution is as follows:
1. When branching with a conditional branch instruction: BT and BF instructions
2. When branching with a delayed conditional branch instruction: BT/S and BF/S instructions
Thus, when a conditional branch instruction or TRAPA instruction causes a branch, the branch
destination instruction will be fetched after an overrun fetch of the next instruction or the
instruction after the next. However, as the instruction that is the object of the break does not break
until fetching and execution of the instruction have been confirmed, the overrun fetches described
above do not become objects of a break.
If data accesses are also included in break conditions besides instruction fetch, a break will occur
because the instruction overrun fetch is also regarded as satisfying the data break condition.
When branching with a TRAPA instruction:
a. Instruction fetch order
b. Instruction execution order
a. Instruction fetch order
b. Instruction execution order
Branch instruction fetch → next instruction overrun fetch → overrun fetch of instruction
after the next → branch destination instruction fetch
Branch instruction execution → branch destination instruction execution
Branch instruction fetch → next instruction fetch (delay slot) → overrun fetch of
instruction after the next → branch destination instruction fetch
Branch instruction execution → delay slot instruction execution → branch destination
instruction execution
Usage Notes
Simultaneous Fetching of Two Instructions
Instruction Fetches at Branches
Rev.4.00 Mar. 27, 2008 Page 111 of 882
TRAPA instruction
7. User Break Controller (UBC)
REJ09B0108-0400
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