HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 312

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.
For details of PWM modes, see section 11.4.5, PWM Modes.
11.4.3
Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 11.29 shows the register combinations used in buffer operation.
Table 11.29 Register Combinations in Buffer Operation
Rev.4.00 Mar. 27, 2008 Page 266 of 882
REJ09B0108-0400
Channel
0
3
4
Multi-Function Timer Pulse Unit (MTU)
Buffer Operation
TGRB_0
TGRB_1
TGRA_0
TGRB_2
TGRA_1
TGRA_2
H'0000
TIOC0A
TIOC1A
TIOC2A
TCNT0 to TCNT2
values
Figure 11.12
Timer General Register
TGRA_0
TGRB_0
TGRA_3
TGRB_3
TGRA_4
TGRB_4
Example of Synchronous Operation
Synchronous clearing by TGRB_0 compare match
Buffer Register
TGRC_0
TGRD_0
TGRC_3
TGRD_3
TGRC_4
TGRD_4
Time