HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 718

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

19. Flash Memory (F-ZTAT Version)
Table 19.4 Boot Mode Operation
Item
Boot mode
start
Bit rate
adjustment
Transfer of
programming
control
program
Flash
memory
erase
Table 19.5 Peripheral Clock (Pφ) Frequencies for which Automatic Adjustment of LSI Bit
Rev.4.00 Mar. 27, 2008 Page 672 of 882
REJ09B0108-0400
Host Bit Rate
9,600 bps
19,200 bps
Host Operation
Processing Contents
Transmits data H'55 when
data H'00 is received
error-free.
Transmits number of bytes (N)
of programming control as
program to be transferred
2-byte data (lower byte
following upper byte)
Continuously transmits data
H'00 at specified bit rate.
Receives data H'AA.
Transmits 1-byte of
programming control program
(repeated for N times)
Rate Is Possible
Receives data H'AA.
Boot program
erase error
Peripheral Clock Frequency Range of LSI
4 to 40 MHz
8 to 40 MHz
Communications Contents
H'00, H'00 ...... H'00
Upper byte and
lower byte
Echoback
Echoback
H'AA
H'XX
H'00
H'55
H'AA
H'FF
LSI Operation
Processing Contents
Branches to boot program at
reset-start.
• Measures low-level period of receive
• Calculates bit rate and sets it in BRR
• Transmits data H'00 to host as
Echobacks the 2-byte data received.
Echobacks received data to host and
also transfers it to RAM (repeated
for N times)
Checks flash memory data, erases all
flash memory blocks in case of written
data existing, and transmits data H'AA
to host. (If erase could not be done,
transmits data H'FF to host and
aborts operation.)
Branches to programming control
program transferred to on-chip RAM
and starts execution.
Transmits data H'AA to host when
data H'55 is received.
data H'00.
of SCI_1.
adjustment end indication.
Boot program initiation