HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 55

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Type
System
control
Interrupts
Address bus A21 to A0
Data bus
Symbol
RES
MRES
WDTOVF
BREQ
BACK
NMI
IRQ7 to IRQ0 Input
IRQOUT
SH7144:
D15 to D0
SH7145:
D31 to D0
I/O
Input
Input
Output
Input
Output
Input
Output
Output
Input/
Output
Name
Power on
reset
Manual reset
Watchdog
timer overflow
Bus request
Bus
acknowledge
Non-maskable
interrupt
Interrupt
request 7 to 0
Interrupt
request output
Address bus
Data bus
Function
When this pin is driven low, the chip
becomes to power on reset state.
When this pin is driven low, the chip
becomes to manual reset state.
Output signal for the watchdog timer
overflow.
If this pin needs to be pulled-down, the
resistance value must be 1 MΩ or higher.
External device can request the release of
the bus mastership by setting this pin low.
Shows that the bus mastership has been
released for the external device. The
device that had issued the BREQ signal
can know that bus mastership has been
released for itself by receiving the BACK
signal.
Non-maskable interrupt pin. If this pin is
not used, it should be fixed high or low.
These pins request a maskable interrupt.
One of the level input or edge input can be
selected In case of the edge input, one of
the rising edge, falling edge, or both can
be selected.
Shows that an interrupt cause has
occurred. The interrupt cause can be
recognized even in the bus release state.
Output the address.
SH7144: Bi-directional 16-bit bus
SH7145: Bi-directional 32-bit bus
Rev.4.00 Mar. 27, 2008 Page 9 of 882
REJ09B0108-0400
1. Overview