HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 199

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.5.4
WCR2 is a 16-bit readable/writable register that specifies the number of access cycles to the CS
space in DMA single address mode transfer.
Do not perform DMA single address transfer before setting WCR2.
9.5.5
RAMER is a 16-bit readable/writable register that selects the RAM area to be used when
emulating realtime programming of flash memory. For details, refer to section 19.5.5, RAM
Emulation Register (RAMER).
Bit
15 to 4 ⎯
3
2
1
0
Bit Name Initial Value
DSW3
DSW2
DSW1
DSW0
Wait Control Register 2 (WCR2)
RAM Emulation Register (RAMER)
All 0
1
1
1
1
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of wait cycles for access to CS space in DMA
single address mode
These bits specify the number of wait cycles (0 to 15)
for access to the CS space in DMA single address
mode. These bits are independent of the W bit in
WCR1.
0000: No wait (external wait insertion disabled)
0001: One wait (external wait insertion enabled)
1111: 15 waits (external waits insertion enabled)
:
Rev.4.00 Mar. 27, 2008 Page 153 of 882
9. Bus State Controller (BSC)
REJ09B0108-0400