HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 171

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note:
8.3.3
Register information is stored in an on-chip RAM. When activated, the DTC reads register
information in an on-chip RAM and transfers data. After the data transfer, it writes updated
register information back to the RAM.
Pre-storage of register information in the RAM makes it possible to transfer data over any required
number of channels. The transfer mode can be specified as normal, repeat, and block transfer
mode. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single
activation source (chain transfer).
Activating
Source
Generator
SCI0
SCI1
Reserved
A/D converter
(CH1)
Reserved
SCI2
SCI3
Reserved
IIC
Reserved
Software
*
DTC Operation
External memory, memory-mapped external devices, on-chip memory, on-chip
peripheral modules (excluding DMAC and DTC)
Activating
Source
RXI_0
TXI_0
RXI_1
TXI_1
—
ADI1
—
RXI_2
TXI_2
RXI_3
TXI_3
—
ICI
—
Write to
DTCSR
DTC Vector
Address
H'00000438
H'0000043A
H'0000043C
H'0000043E
H'00000440 to
H'00000443
H'00000444
H'00000446
H'00000448
H'0000044A
H'0000044C
H'0000044E
H'00000450 to
H'0000045F
H'00000460
H'00000462 to
H'0000049F
H'0400+
DTVEC[7:0]
DTE Bit
DTED3
DTED2
DTED1
DTED0
—
DTEE5
—
DTEE3
DTEE2
DTEE1
DTEE0
—
DTEG7
—
—
Rev.4.00 Mar. 27, 2008 Page 125 of 882
Transfer
Source
RDR_0
Arbitrary*
RDR_1
Arbitrary*
—
ADDR1
—
RDR_2
Arbitrary*
RDR_3
Arbitrary*
—
ICDR
(receive)
Arbitrary*
(transmit)
—
Arbitrary*
8. Data Transfer Controller (DTC)
Transfer
Destination
Arbitrary*
TDR_0
Arbitrary*
TDR_1
—
Arbitrary*
—
Arbitrary*
TDR_2
Arbitrary*
TDR_3
—
Arbitrary*
(receive)
ICDR
(transmit)
—
Arbitrary*
REJ09B0108-0400
Priority
High
Low