HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 182

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8. Data Transfer Controller (DTC)
8.5
8.5.1
DMAC and DTC register access by the DMAC is prohibited.
8.5.2
DTC operation can be disabled or enabled using the module standby control register. The initial
setting is for DTC operation to be halted. Register access is enabled by clearing module standby
mode.
When the MSTP24 and MSTP25 bits in MSTCR1 are set to 1, the DTC clock is halted and the
DTC enters module standby mode. The MSTP24 and MSTP25 bit cannot be set to 1 during
activation of the DTC.
In addition, when the module standby mode is entered, clear all the DTER bits to 0.
For details, refer to section 24, Power-Down Modes.
8.5.3
The DTMR, DTSAR, DTDAR, DTCRA,DTCRB and DTIAR registers are all located in on-chip
RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0.
Rev.4.00 Mar. 27, 2008 Page 136 of 882
REJ09B0108-0400
Usage Notes
Prohibition against DMAC/DTC Register Access by DTC
Module Standby Mode Setting
On-Chip RAM