HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 535

IC SUPERH MCU ROMLESS 112QFP

HD6417144F50V

Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet

Specifications of HD6417144F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Note:
Bit
0
Bit Name Initial Value R/W
ACKB
*
Only 0 can be written to clear the flag.
0
R/W
Acknowledge
This bit stores the acknowledgements.
Transmit mode:
[Setting condition]
[Clearing conditions]
Receive mode:
0: After reception of data, 0 is output as acknowledge data
1: After reception of data, 1 is output as acknowledge data
When this bit is read, the value that was loaded here (the
value returned from the receiving device) is read during
transmission (TRS = 1). During receive operations (TRS =
0), the value that was set is read.
When this bit is written, acknowledge data that is returned
after receiving is rewritten regardless of the TRS value. If
the ICSR register flag is written using bit-manipulation
instructions, the acknowledge data should be set again
since the acknowledge data setting is rewritten by the
reading value of ACKB bit.
Write the ACKE bit to 0 to clear the ACKB flag to 0, before
transmission is ended and a stop condition is issued in
master mode, or before transmission is ended and SDA is
released to issue a stop condition by a master device.
Description
Reception of 1 as an acknowledge bit when ACKE is 1
in transmit mode.
Reception of 0 as an acknowledge bit when ACKE is 1
in transmit mode.
Writing 0 to the ACKE bit
Rev.4.00 Mar. 27, 2008 Page 489 of 882
14. I
2
C Bus Interface (IIC) Option
REJ09B0108-0400

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