HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 366

IC SUPERH MCU ROMLESS 112QFP

HD6417144F50V

Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet

Specifications of HD6417144F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
11.
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC/DMAC is activated, the flag is cleared automatically. Figure 11.68 shows
the timing for status flag clearing by the CPU, and figure 11.69 shows the timing for status flag
clearing by the DTC/DMAC.
Rev.4.00 Mar. 27, 2008 Page 320 of 882
REJ09B0108-0400
Multi-Function Timer Pulse Unit (MTU)
Figure 11.69
Address
Write signal
Status flag
Interrupt
request signal
Address
Status flag
Interrupt
request signal
Figure 11.68
Timing for Status Flag Clearing by DTC/DMAC Activation
Timing for Status Flag Clearing by CPU
TSR write cycle
Source address
DTC/DMAC
TSR address
T1
read cycle
T1
T2
T2
DTC/DMAC
T1
write cycle
Destination
address
T2

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