HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 747

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Serial data
H-UDI interrupt
request
SDTRF
(in SDSR) *
SDSR and SDDR
MUX *
SDDR access
state
Notes: 1. SDTRF flag (in SDSR): Indicates whether SDDR access by the CPU or serial transfer
2
2. SDSR/SDDR (Update-DR state) internal MUX switchover timing
1
data input/output to SDDR is possible.
Conditions: • SDTRF = 1
• Switchover from SDSR to SDDR: On completion of serial transfer in which
• Switchover from SDDR to SDSR: On completion of serial transfer to SDDR
1
0
SDTRF = 1 is output from TDO
Figure 22.2 Data Input/Output Timing Chart (1)
SDDR is shift-enabled. Do not access SDDR until SDTRF = 0.
SDDR is shift-disabled. SDDR access by the CPU is enabled.
Shift
enabled
• SDTRF = 0
— When TRST = 0
— When the CPU writes 1
— In bypass mode
— End of SDDR shift access in serial transfer
Instruc-
tion
Shift
SDSR
SDTRF
1
SDDR
Input
disabled
Rev.4.00 Mar. 27, 2008 Page 701 of 882
CPU
Shift
0
22. User Debugging Interface (H-UDI)
SDSR
SDSR serial transfer
Shift
enabled
1
(monitoring)
Shift
SDDR
output
Input/
REJ09B0108-0400
CPU