HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 500

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13. Serial Communication Interface (SCI)
13.7.4
In smart card interface mode an internal clock generated by the on-chip baud rate generator can
only be used as a transmit/receive clock. In this mode, the SCI operates on a basic clock with a
frequency of 32, 64, 372, or 256 times the bit rate (fixed to 16 times in normal asynchronous
mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the falling edge of
the start bit using the basic clock, and performs internal synchronization. As shown in figure
13.25, by sampling receive data at the rising edge of the 16th, 32nd, 186th, or 128th pulse of the
basic clock, data can be latched at the middle of the bit. The reception margin is given by the
following formula.
Where M: Reception margin (%)
Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
Rev.4.00 Mar. 27, 2008 Page 454 of 882
REJ09B0108-0400
= 49.866%
Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode
Receive Data Sampling Timing and Reception Margin
M = | (0.5 –
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
2N
1
) – (L – 0.5) F –
186 clocks
0
(Using Clock of 372 Times Bit Rate)
185
372 clocks
Start bit
371
| D – 0.5 |
0
N
D0
(1 + F) | × 100%
185
371 0
D1