HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 421

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note:
11.9.4
Input Level Detection Operation:
If the input conditions set by the ICSR1 occur on any of the POE pins, all high-current pins
become high-impedance state. Note however, that these high-current pins become high-impedance
state only when general input/output function or MTU function is selected in these pins.
1. Falling Edge Detection
2. Low-Level Detection
Bit
8
7 to 0 ⎯
When a change from high to low level is input to the POE pins.
Figure 11.115 shows the low-level detection operation. Sixteen continuous low levels are
sampled with the sampling clock established by the ICSR1. If even one high level is detected
during this interval, the low level is not accepted.
Sampling starts when detecting the falling edge of the POE pin. Thereby, negate the POE pin
when using POE function after sampling.
Furthermore, the timing when the large-current pins enter the high-impedance state from the
sampling clock is the same in both falling-edge detection and in low-level detection.
Bit Name
OIE
*
Operation
Only 0 can be written to write the flag.
Initial value
0
All 0
R/W
R
R/W
Description
Output Short Interrupt Enable
This bit makes interrupt requests when the OSF bit
of the OCSR is set.
00: Interrupt requests disabled
01: Interrupt request enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
11.
Rev.4.00 Mar. 27, 2008 Page 375 of 882
Multi-Function Timer Pulse Unit (MTU)
REJ09B0108-0400