HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 140

• Manufacturer Part Number: HD64F2145BTE20
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2145BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 4 Exception Handling
4.3.2
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
After a reset is cancelled, the module stop control registers (MSTPCR) are initialized, and all
modules except the DTC operate in module stop mode. Therefore, the registers of on-chip
peripheral modules cannot be read from or written to. To read from and write to these registers,
clear module stop mode.
Rev. 3.00 Mar 21, 2006 page 84 of 788
REJ09B0300-0300
Interrupts after Reset
On-Chip Peripheral Modules after Reset Is Cancelled
RES
Internal address bus
Internal read signal
Internal write signal
Internal data bus
(1) Reset exception handling vector address ((1) = H'0000)
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2))
(4) First program instruction
Figure 4.1 Reset Sequence (Mode 3)
Vector
fetch
(1)
(2)
processing
Internal
High
Prefetch of first program
instruction
(3)
(4)