HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 602

• Manufacturer Part Number: HD64F2145BTE20
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2145BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 19 Host Interface LPC Interface (LPC)
Bits 15 to 4
0000 0000 0110
0000 0000 0110
Bit
7
6
5
4
3
2
1
Rev. 3.00 Mar 21, 2006 page 546 of 788
REJ09B0300-0300
STR1
Bit Name Initial Value Slave Host Description
DBU17
DBU16
DBU15
DBU14
C/D1
DBU12
IBF1
0
0
0
0
0
0
0
I/O Address
Bit 3
0
0
Bit 2
1
1
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R
R
R
R
R
R
0
1
Bit 1
Defined by User
The user can use these bits as necessary.
Command/Data
When the host processor writes to an IDR register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
Defined by User
The user can use this bit as necessary.
Input Buffer Full
Set to 1 when the host processor writes to IDR. This
bit is an internal interrupt source to the slave
processor (this LSI). IBF is cleared to 0 when the
slave processor reads IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details
see table 19.3.
0: [Clearing condition]
When the slave processor reads IDR
1: [Setting condition]
When the host processor writes to IDR using I/O
write cycle
Bit 0
0
0
Transfer
Cycle
I/O read
I/O read
Host Register Selection
STR1 read
STR2 read