HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 222

• Manufacturer Part Number: HD64F2145BTE20
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2145BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 Data Transfer Controller (DTC)
7.8
7.8.1
DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the
initial state, DTC operation is enabled. Access to DTC registers are disabled when module stop
mode is set. Note that when the DTC is being activated, module stop mode cannot be specified.
For details, refer to section 26, Power-Down Modes.
7.8.2
MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM. When the DTC is used,
the RAME bit in SYSCR should not be cleared to 0.
7.8.3
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR, for reading and
writing. Multiple DTC activation sources can be set at one time (only at the initial setting) by
masking all interrupts and writing data after executing a dummy read on the relevant register.
7.8.4
Set the MSTP14 bit in MSTPCRH to 1 to make the DTC enter module stop mode, then confirm
that is set to 1 before making a transition to subactive mode or watch mode.
7.8.5
Interrupt sources of the SCI, IIC, LPC, or A/D converter which activate the DTC are cleared when
DTC reads from or writes to the respective registers, and they cannot be cleared by the DISEL bit
in MRB.
Rev. 3.00 Mar 21, 2006 page 166 of 788
REJ09B0300-0300
Usage Notes
Module Stop Mode Setting
On-Chip RAM
DTCE Bit Setting
Setting Required on Entering Subactive Mode or Watch Mode
DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter